US 11,775,430 B1
Memory access for multiple circuit components
Ron Diamant, Santa Clara, CA (US); Sundeep Amirineni, Austin, TX (US); Akshay Balasubramanian, Austin, TX (US); and Eyal Freund, Austin, TX (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Aug. 24, 2020, as Appl. No. 17/842.
Application 17/000,842 is a continuation of application No. 15/919,167, filed on Mar. 12, 2018, granted, now 10,768,856, issued on Sep. 8, 2020.
Int. Cl. G06F 12/08 (2016.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G06N 3/063 (2023.01)
CPC G06F 12/08 (2013.01) [G06N 3/063 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first port and a second port; and
a read access engine configured to:
receive, from a first access requester device, a first read request to fetch first data stored at a memory device;
receive, from a second access requester device, a second read request to fetch second data stored at the memory device;
provide, via the first port, a sequential access of a plurality of portions of the first data to the first access requester device by:
receiving the plurality of portions of the first data from the memory device during a first single clock cycle and outputting the plurality of portions of the first data to the first access requester device during multiple clock cycles;
provide, via the second port, a sequential access of a plurality of portions of the second data to the second access requester device by:
receiving the plurality of portions of the second data from the memory device during a second single clock cycle and outputting the plurality of portions of the second data to the first access requester device during the multiple clock cycles, wherein the second single clock cycle is after the first single clock cycle, and wherein the multiple clock cycles are after the second single clock cycle.