CPC G06F 9/546 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30145 (2013.01); G06F 9/321 (2013.01); G06F 9/542 (2013.01)] | 13 Claims |
1. A method for inter-enclave communication via cache memory of a processor, the method comprising:
instantiating a first enclave such that the first enclave is configured to execute a first communication thread, which is configured to read or write data to the cache memory;
instantiating a second enclave such that the second enclave is configured to execute a second communication thread, which is configured to read or write data to cache memory;
executing, by the first enclave, the first communication thread to send message data to the second enclave, executing the first communication thread comprising writing the message data to the cache memory; and
executing, by the second enclave, the second communication thread to receive the message data, executing the second communication thread comprising:
monitoring the cache memory to determine whether the data message is being sent; and
based upon determining the data message is being sent, reading from the cache memory to receive the data message,
wherein the cache memory comprises a plurality of cache sets,
wherein the method comprises:
designating one of the cache sets as a signaling cache set; and
designating N of the cache sets as N communication cache sets, and
wherein executing the first communication thread comprises writing on the signaling cache set to notify the second enclave that the message data is being transmitted.
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