US 11,775,302 B2
Histogram operation
Naveen Bhoria, Plano, TX (US); Duc Bui, Grand Prairie, TX (US); Rama Venkatasubramanian, Plano, TX (US); Dheera Balasubramanian Samudrala, Richardson, TX (US); and Alan Davis, Sugar Land, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 25, 2021, as Appl. No. 17/509,218.
Application 17/509,218 is a continuation of application No. 16/570,931, filed on Sep. 13, 2019, granted, now 11,157,278.
Claims priority of provisional application 62/853,120, filed on May 27, 2019.
Prior Publication US 2022/0043655 A1, Feb. 10, 2022
Int. Cl. G06F 9/30 (2018.01); G11C 11/409 (2006.01); G06F 12/02 (2006.01); G06F 9/38 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30007 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30105 (2013.01); G06F 9/3818 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G11C 11/409 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a cache configured to store a set of tables; and
a set of registers that includes a first register configured to store a set of indices each corresponding to a respective value stored in a respective table of the set of tables, wherein the processor is configured to:
receive an instruction that specifies the first register and the set of tables; and
based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables.