CPC G06F 9/30145 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30007 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30105 (2013.01); G06F 9/3818 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G11C 11/409 (2013.01)] | 20 Claims |
1. A processor comprising:
a cache configured to store a set of tables; and
a set of registers that includes a first register configured to store a set of indices each corresponding to a respective value stored in a respective table of the set of tables, wherein the processor is configured to:
receive an instruction that specifies the first register and the set of tables; and
based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables.
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