CPC G06F 9/30123 (2013.01) [G06F 9/3009 (2013.01); G06F 9/384 (2013.01); G06F 9/3877 (2013.01); G06F 15/80 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a plurality of processors configured to execute processor instructions; and
a coprocessor configured to decode and execute coprocessor instructions, wherein ones of the plurality of processors are configured to provide the coprocessor instructions to the coprocessor, and wherein the coprocessor includes:
an operand register set configured to store operands for coprocessor instructions to be executed;
an array of processing elements;
a result register set comprising storage elements respectively distributed within the array of processing elements, wherein for a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member; and
rename logic circuitry configured to monitor active contexts corresponding to the plurality of processors;
wherein the result register set implements a plurality of contexts configured to store respective coprocessor states corresponding to coprocessor instructions received from different ones of the plurality of processors;
wherein the rename logic circuitry is further configured to track which portions of a particular register of the result register set were used during execution of a particular instruction, and to identify an inactive context in response to detecting that at least a portion of the particular register of the result register set has been written as logic zeros; and
wherein, based on a determination that a one of the plurality of contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the one of the plurality of contexts that is inactive.
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