CPC G06F 9/30036 (2013.01) [G06F 9/3887 (2013.01)] | 22 Claims |
1. A processor, comprising:
a plurality of cores, wherein at least a portion of the plurality cores can be selectively configured and comprise,
a first block of circuitry configured to implement an instruction set architecture (ISA) supporting a first set of instructions; and
one or more ISA extension units comprising circuitry separate from the first block of circuitry configured to implement a second set of instructions comprising one or more extended instructions that are not included in the first set of instructions, wherein the ISA extension unit can be selectively enabled or disabled,
wherein the plurality of cores include power frequency control logic that enables the clock frequency of the cores to be dynamically adjusted on a per-core basis.
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