US 11,775,298 B2
Frequency scaling for per-core accelerator assignments
Stephen T. Palermo, Chandler, AZ (US); Srihari Makineni, Portland, OR (US); Shubha Bommalingaiahnapallya, East Brunswick, NJ (US); Neelam Chandwani, Portland, OR (US); Rany T. Elsayed, Folsom, CA (US); Udayan Mukherjee, Portland, OR (US); Lokpraveen Mosur, Gilbert, AZ (US); and Adwait Purandare, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 20, 2020, as Appl. No. 16/933,369.
Claims priority of provisional application 63/015,083, filed on Apr. 24, 2020.
Prior Publication US 2021/0334101 A1, Oct. 28, 2021
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3887 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor, comprising:
a plurality of cores, wherein at least a portion of the plurality cores can be selectively configured and comprise,
a first block of circuitry configured to implement an instruction set architecture (ISA) supporting a first set of instructions; and
one or more ISA extension units comprising circuitry separate from the first block of circuitry configured to implement a second set of instructions comprising one or more extended instructions that are not included in the first set of instructions, wherein the ISA extension unit can be selectively enabled or disabled,
wherein the plurality of cores include power frequency control logic that enables the clock frequency of the cores to be dynamically adjusted on a per-core basis.