US 11,775,268 B1
Color selection schemes for storage allocation
Preston Pengra Briggs, Seattle, WA (US); Ron Diamant, Santa Clara, CA (US); and Robert Geva, Cupertino, CA (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Jun. 8, 2021, as Appl. No. 17/341,762.
Int. Cl. G06F 8/41 (2018.01); G06F 12/06 (2006.01); G06F 9/30 (2018.01)
CPC G06F 8/41 (2013.01) [G06F 8/441 (2013.01); G06F 9/30123 (2013.01); G06F 12/0646 (2013.01); G06F 2212/1024 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A computer-program product tangibly embodied in a non-transitory machine-readable storage medium, the computer-program product including instructions configured to cause a processor to perform operations for executing a compiler, the operations comprising:
receiving computer code to be converted into machine instructions for execution on an integrated circuit device, the integrated circuit device including a memory having a set of memory locations;
determining, based on the computer code, a set of values that are to be stored on the integrated circuit device during the execution of the machine instructions on the integrated circuit device;
constructing an interference graph that includes the set of values and a set of interferences that indicate which of the set of values are concurrently stored during the execution of the machine instructions;
traversing the interference graph in order to generate a set of memory location assignments by:
performing a simplification process of the interference graph in accordance with a first order;
performing a rebuilding process of the interference graph in accordance with a second order determined from the first order, wherein the performing the rebuilding process comprises, for each value of the set of values:
determining if a switch condition is satisfied, wherein determining that the switch condition is satisfied includes determining whether the value of the set of values is defined by a low-latency instruction or a high-latency instruction;
if the value is defined by a low-latency instruction, assigning the value to a first memory location of the set of memory locations in accordance with a first color selection scheme; and
if the value is defined by a high-latency instruction, assigning the value to a second memory location of the set of memory locations in accordance with a second color selection scheme, wherein the second color selection scheme is different from the first color selection scheme; and
generating the machine instructions based on the computer code while incorporating the set of memory location assignments for each value of the set of values, wherein the generated machine instructions cause the integrated circuit device to store the set of values at the set of memory locations in the memory as specified in the set of memory location assignments when the machine instructions are read and executed on the integrated circuit device.