US 11,775,219 B2
Access control structure for shared memory
Wei Ze Liu, Spring, TX (US); Khoa Dang Huynh, Houston, TX (US); and Rosilet Retnamoni Braduke, Cypress, TX (US)
Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US)
Filed by Hewlett-Packard Development Company, L.P., Spring, TX (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,251.
Prior Publication US 2023/0229351 A1, Jul. 20, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0632 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a flash memory;
a host memory to store an access control structure to access the flash memory; and
a first circuitry coupled to the host memory and the flash memory, wherein the first circuitry is to read a status of the flash memory in the access control structure in the host memory to determine when to access the flash memory, and
wherein the access control structure comprises the status, a component quantity, and a set of addresses for component blocks.