US 11,775,199 B2
Voltage resonance mitigation of memory dies
Fuad Badrieh, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 20, 2021, as Appl. No. 17/153,519.
Prior Publication US 2022/0229579 A1, Jul. 21, 2022
Int. Cl. G11C 11/4074 (2006.01); G06F 3/06 (2006.01); G11C 5/14 (2006.01); G11C 11/22 (2006.01); G11C 16/22 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01); G11C 5/143 (2013.01); G11C 11/225 (2013.01); G11C 16/225 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
monitoring a voltage of a memory die with a controller positioned on the memory die;
analyzing, with the controller positioned on the memory die, a frequency response of the monitored voltage;
detecting, with the controller positioned on the memory die, a frequency at which the monitored voltage resonates;
detecting that a value of the voltage at the frequency satisfies a threshold associated with the resonance; and
performing, with the controller positioned on the memory die, an operation to mitigate the resonance of the monitored voltage at the frequency based at least in part on the frequency response analyzed by the controller positioned on the memory die and the frequency detected by the controller positioned on the memory die, wherein the operation to mitigate the resonance further comprises delaying a start time of access operations in a command queue of the memory die.