US 11,775,198 B2
Data erasure in memory sub-systems
Kevin R Brandt, Boise, ID (US); and Thomas Cougar Van Eaton, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 18, 2021, as Appl. No. 17/529,908.
Application 17/529,908 is a continuation of application No. 16/824,335, filed on Mar. 19, 2020, granted, now 11,237,755.
Application 16/824,335 is a continuation of application No. 16/148,564, filed on Oct. 1, 2018, granted, now 10,628,076.
Prior Publication US 2022/0075549 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); H04L 9/08 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/064 (2013.01); G06F 3/0608 (2013.01); G06F 3/0688 (2013.01); H04L 9/0891 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory component comprising a plurality of blocks; and
a processing device programmed to perform operations comprising:
receiving a sanitize command for the plurality of blocks, wherein a first portion of the plurality of blocks are retired and a second portion of the plurality of blocks are unretired;
initiating an erase cycle at a retired block of the plurality of blocks;
determining that the erase cycle was successful; and
indicating that the sanitize command was successful.