US 12,433,032 B2
Semiconductor structure including boundary header cell and method for manufacturing the same
Hao-Tien Kan, New Taipei (TW); Yan-Shen You, Taoyuan (TW); Chin-Shen Lin, Taipei (TW); Kuo-Nan Yang, Hsinchu (TW); and Chung-Hsing Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Feb. 15, 2022, as Appl. No. 17/672,010.
Prior Publication US 2023/0260984 A1, Aug. 17, 2023
Int. Cl. H10D 89/10 (2025.01); H10D 84/85 (2025.01); G06F 30/30 (2020.01); G11C 5/14 (2006.01); H03K 19/00 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01)
CPC H10D 89/10 (2025.01) [H10D 84/854 (2025.01); G06F 30/30 (2020.01); G11C 5/14 (2013.01); H03K 19/0008 (2013.01); H03K 19/0013 (2013.01); H10B 10/00 (2023.02); H10B 12/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first semiconductor device;
a second semiconductor device spaced apart from the first semiconductor device, the first semiconductor device and the second semiconductor device defining a channel region; and
a first semiconductor component disposed in the channel region and configured to control states of a plurality of components in the channel region, wherein the first semiconductor component includes an n-doped region, a p-doped region, and a n-tap adjacent to the p-doped region, wherein the p-doped region and the n-tap are disposed in the n-doped region,
wherein the first semiconductor device and the first semiconductor component are located adjacent to a boundary, and the first semiconductor component is electrically isolated from the first semiconductor device,
wherein the n-doped region of the first semiconductor component is an n-type well, and the first semiconductor component includes a p-type well, and the n-tap is located between the p-doped region and the p-type well.