| CPC H10D 84/834 (2025.01) [H01L 21/76897 (2013.01); H10D 30/6219 (2025.01)] | 19 Claims |
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1. A semiconductor device comprising:
a fin type active pattern extending in a first direction;
a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs respectively between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of the gate insulation layer and the side surface of the gate capping layer;
a second spacer on a side surface of the first spacer; and
a plurality of gate layers sequentially stacked apart from one another on a lower portion of the gate insulation layer,
wherein an upper surface of the second spacer is asymmetrical with respect to a center axis extending in a vertical direction perpendicular to the first and second directions of the inter-contact insulation patterns,
wherein the gate capping layer is free from overlap by the plurality of contact plugs in the vertical direction,
wherein an uppermost surface of the gate capping layer is concavely recessed,
wherein each of the plurality of inter-contact insulation patterns is disposed on the gate capping layer, the first spacer, and the second spacer, and
wherein a bottom surface of each of the plurality of inter-contact insulation patterns protrudes downward toward the first gate metal and the second gate metal.
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