| CPC H10D 62/151 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active region on a substrate;
source/drain patterns on the active region;
channel patterns on the active region and connected to the source/drain patterns, each of the channel patterns comprising a plurality of semiconductor patterns vertically stacked to be spaced apart from each other;
gate electrodes, which are respectively on the channel patterns and are extended in a first direction and parallel to each other; and
active contacts, which are electrically and respectively connected to the source/drain patterns,
wherein the active region comprises a first region having a first width, a second region having a second width, and a third region having a third width,
the first width is larger than the third width,
the third width is larger than the second width,
the third region is interposed between the first region and the second region,
the source/drain patterns comprise a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern on the first, second, and third regions, respectively,
the active contacts comprise a first active contact, a second active contact, and a third active contact respectively electrically connected to the first, second, and third source/drain patterns,
a bottom surface of the first active contact is at a first level,
a bottom surface of the second active contact is at a second level higher than the first level, and
a bottom surface of the third active contact is at a third level higher than the second level.
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