US 12,432,983 B2
Thin-film transistor device
Po-Tsun Liu, Hsinchu (TW); Zhen-Hao Li, Tainan (TW); Tsung-Che Chiang, Taoyuan (TW); and Po-Yi Kuo, Hengchun Township (TW)
Assigned to National Yang Ming Chiao Tung University, Hsinchu (TW)
Filed by National Yang Ming Chiao Tung University, Hsinchu (TW)
Filed on Oct. 12, 2022, as Appl. No. 18/045,878.
Claims priority of application No. 110145689 (TW), filed on Dec. 7, 2021.
Prior Publication US 2023/0178660 A1, Jun. 8, 2023
Int. Cl. H10D 30/67 (2025.01)
CPC H10D 30/6757 (2025.01) [H10D 30/6745 (2025.01); H10D 30/6756 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A thin-film transistor device, comprising:
a substrate;
a first thin-film structure disposed on said substrate, and including
a channel layer containing polycrystalline silicon,
a first source layer disposed at one side of said channel layer and containing polycrystalline silicon, and
a first drain layer disposed at the other side of said channel layer opposite to said first source layer and containing polycrystalline silicon;
a gate structure disposed on said first thin-film structure, and including
a common gate electrode disposed on and positioned in correspondence with said channel layer of said first thin-film structure, and
a gate insulating layer that wraps said common gate electrode and that covers said first thin-film structure; and
a second thin-film structure disposed on said gate structure, and including
an active layer disposed on said gate insulating layer and positioned in correspondence with said common gate electrode of said gate structure,
a second source layer disposed at one side of said active layer, and
a second drain layer disposed at the other side of said active layer opposite to said second source layer,
wherein
said active layer includes an indium oxide-based material that is at least doped with tungsten oxide,
said second drain layer extends through said gate insulating layer and is electrically connected to said first drain layer, and
said first source layer and said second source layer are electrically insulated by said gate insulating layer.