US 12,432,982 B2
Multi-channel transistor and manufacturing method by the same
Tae Yeon Seong, Seoul (KR); and Kwang Ro Yun, Seoul (KR)
Assigned to KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Appl. No. 17/777,692
Filed by KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
PCT Filed Nov. 18, 2020, PCT No. PCT/KR2020/016261
§ 371(c)(1), (2) Date May 18, 2022,
PCT Pub. No. WO2021/101242, PCT Pub. Date May 27, 2021.
Claims priority of application No. 10-2019-0148038 (KR), filed on Nov. 18, 2019; and application No. 10-2020-0153705 (KR), filed on Nov. 17, 2020.
Prior Publication US 2022/0406946 A1, Dec. 22, 2022
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 88/00 (2025.01)
CPC H10D 30/6757 (2025.01) [H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 88/00 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A multilayer-channel thin-film transistor, comprising:
a first channel layer formed on a substrate;
a first source electrode and first drain electrode formed on the first channel layer;
a first gate insulating film formed on the first channel layer, the first source electrode and the first drain electrode;
a gate electrode formed on the first gate insulating film;
a second gate insulating film formed on the gate electrode;
a second channel layer formed on the second gate insulating film; and
a second source electrode and second drain electrode formed on the second channel layer,
wherein the first source electrode and the second source electrode are electrically connected to each other through a source electrode connection part, and the first drain electrode and the second drain electrode are electrically connected to each other through a drain electrode connection part, and
wherein the gate electrode is buried in the second gate insulating film.