US 12,432,981 B2
Transistor, method of manufacturing transistor, and display device using the same
Sakae Tanaka, Saitama (JP)
Assigned to MIKUNI ELECTRON CORPORATION, Saitama (JP)
Filed by Mikuni Electron Corporation, Saitama (JP)
Filed on May 30, 2024, as Appl. No. 18/678,553.
Application 18/678,553 is a continuation of application No. 18/447,360, filed on Aug. 10, 2023, granted, now 12,113,134.
Application 18/447,360 is a continuation of application No. 17/572,789, filed on Jan. 11, 2022, granted, now 11,929,439, issued on Mar. 12, 2024.
Application 17/572,789 is a continuation of application No. 16/577,044, filed on Sep. 20, 2019, granted, now 11,257,961, issued on Feb. 22, 2022.
Claims priority of application No. 2018-180487 (JP), filed on Sep. 26, 2018.
Prior Publication US 2024/0322047 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 62/80 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01)
CPC H10D 30/6756 (2025.01) [H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H10D 30/673 (2025.01); H10D 30/6734 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01); H10D 86/451 (2025.01); H10K 59/1201 (2023.02); H10K 59/1213 (2023.02); H10K 59/124 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A transistor comprising:
an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first layer and a second layer;
a first gate electrode including a region overlapping the oxide semiconductor layer;
a first insulating layer between the first gate electrode and the oxide semiconductor layer; and
a first oxide conductive layer and a second oxide conductive layer each including a region in contact with the oxide semiconductor layer;
wherein the first layer of the oxide semiconductor layer and the second layer of the oxide semiconductor layer include a region overlapping each other, the first layer of the oxide semiconductor layer is arranged closer to the top surface of the substrate than the second layer of the oxide semiconductor layer,
wherein a crystallization ratio of the second layer of the oxide semiconductor layer is bigger than a crystallization ratio of the first layer of the oxide semiconductor layer.