US 12,432,979 B2
Gate dielectric for thin film oxide transistors
Christopher Connor, Hillsboro, OR (US); James O'Donnell, Forest Grove, OR (US); and Shailesh Kumar Madisetti, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 15, 2021, as Appl. No. 17/476,165.
Prior Publication US 2023/0080212 A1, Mar. 16, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 99/00 (2025.01); H01L 21/77 (2017.01)
CPC H10D 30/6755 (2025.01) [H10D 30/6757 (2025.01); H10D 99/00 (2025.01); H01L 21/77 (2013.01); H10D 30/0278 (2025.01); H10D 30/6728 (2025.01)] 20 Claims
OG exemplary drawing
 
16. An integrated circuit, comprising:
a gate electrode;
a first layer comprising a semiconductor material;
a second layer between the first layer and the gate electrode, and in contact with the first layer, the second layer comprising a crystalline high-k dielectric material, wherein hydrogen is stacked up at an interface between the gate electrode and the second layer;
a first contact coupled to the first layer at a first location; and
a second contact coupled to the first layer at a second location.