US 12,432,976 B2
Thin film transistors having strain-inducing structures integrated with 2D channel materials
Chelsey Dorow, Portland, OR (US); Kevin P. O'Brien, Portland, OR (US); Carl Naylor, Portland, OR (US); Kirby Maxey, Hillsboro, OR (US); Sudarat Lee, Hillsboro, OR (US); Ashish Verma Penumatcha, Beaverton, OR (US); and Uygar E. Avci, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/481,250.
Prior Publication US 2023/0087668 A1, Mar. 23, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/6743 (2025.01) [H10D 30/751 (2025.01); H10D 64/517 (2025.01)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a two-dimensional (2D) material layer above a substrate;
a gate stack on the 2D material layer, the gate stack having a first side opposite a second side;
a first gate spacer on the 2D material layer and adjacent to the first side of the gate stack;
a second gate spacer on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer induce a strain on the 2D material layer, and wherein the 2D material layer extends vertically beneath the first gate spacer and the second gate spacer;
a first conductive structure on the 2D material layer and adjacent to the first gate spacer; and
a second conductive structure on the 2D material layer and adjacent to the second gate spacer.