| CPC H10D 30/6735 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 64/021 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active pattern provided on a substrate and extending in a first direction;
a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction;
a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns;
a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and
a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns,
wherein the gate spacer comprises a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns,
wherein each of the plurality of first spacer patterns is a semiconductor spacer pattern, and
wherein each of the plurality of second spacer patterns is a dielectric spacer pattern comprising silicon.
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