| CPC H10D 30/6735 (2025.01) [H10D 30/019 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/121 (2025.01); H10D 64/258 (2025.01); H10D 64/667 (2025.01); H10D 84/83 (2025.01); H10D 84/851 (2025.01)] | 18 Claims |
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1. A semiconductor device comprising:
a substrate having a first region and a second region;
a first active fin extending in a first direction in the first region of the substrate;
a plurality of first channel layers disposed on the first active fin and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate;
a first gate pattern intersecting the first active fin and the plurality of first channel layers on the substrate, extending in a second direction, and surrounding at least a portion of the plurality of first channel layers;
a second active fin extending in the first direction in the second region of the substrate;
a plurality of second channel layers disposed on the second active fin and spaced apart from each other in the vertical direction; and
a second gate pattern intersecting the second active fin and the plurality of second channel layers on the substrate, extending in the second direction, and surrounding at least a portion of the plurality of second channel layers,
wherein the first gate pattern comprises a first conductive layer, a first gate dielectric layer interposed between the first conductive layer and each of the plurality of first channel layers, and a second conductive layer on the first conductive layer,
wherein the first conductive layer and the first gate dielectric layer are disposed to fill spaces between the plurality of first channel layers,
wherein the first conductive layer comprises a liner portion disposed on an upper surface of an uppermost first channel layer from among the plurality of first channel layers and that has a first thickness in the vertical direction, and an inner portion disposed in the spaces between the plurality of first channel layers and that has a second thickness in the vertical direction, and
wherein the first thickness is less than 0.5 times the second thickness, and
wherein the semiconductor device further comprises first spacer layers disposed on both sides of the first gate pattern and extending in the second direction,
wherein the first gate dielectric layer conformally covers the upper surface of the uppermost first channel layer and inner side surfaces of the first spacer layers,
wherein the liner portion of the first conductive layer extends in the vertical direction along inner side surfaces of the first gate dielectric layer covering the inner side surfaces of the first spacer layers, wherein a thickness in the first direction of the liner portion on the inner side surfaces of the first gate dielectric layer is substantially equal to the first thickness, and
wherein the thickness in the first direction of the liner portion is a thickness between the inner side surfaces of the first gate dielectric layer and an interface that is present between the first conductive layer and an adjacent layer.
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