US 12,432,969 B2
Array substrate and display device
Jun Wang, Beijing (CN); and Zhonghao Huang, Beijing (CN)
Assigned to Chongqing BOE Optoelectronics Technology Co., Ltd., Chongqing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Chongqing BOE Optoelectronics Technology Co., Ltd., Chongqing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Mar. 22, 2024, as Appl. No. 18/613,390.
Application 18/613,390 is a continuation of application No. 18/134,389, filed on Apr. 13, 2023, granted, now 12,074,222.
Application 18/134,389 is a continuation of application No. 17/199,521, filed on Mar. 12, 2021, granted, now 11,652,172.
Claims priority of application No. 202010663685 (CN), filed on Jul. 10, 2020.
Prior Publication US 2024/0250176 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 29/66 (2006.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6723 (2025.01) [H10D 30/6755 (2025.01); H10D 86/0221 (2025.01); H10D 86/0231 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising a display area and a non-display area located at a periphery of the display area, wherein the array substrate comprises:
a base substrate;
a first metal layer located at one side of the base substrate, the first metal layer comprises a light shielding part, a source; the light shielding part, and the source are located in the display area;
a buffer layer located at a side, facing away from the base substrate, of the first metal layer;
an active layer located at a side, facing away from the first metal layer, of the buffer layer and located in the display area;
a gate insulating layer located at a side, facing away from the buffer layer, of the active layer; and
a second metal layer located at a side, facing away from the active layer, of the gate insulating layer, wherein the second metal layer comprises a gate, a source landing electrode;
the source landing electrode is in contact with the active layer and the source through a first via hole,
wherein the first metal layer further comprises a first signal line located in the non-display area; and
the second metal layer further comprises a second signal line located in the non-display area, wherein the second signal line and the first signal line are conductive through a third via hole penetrating through the gate insulating layer and the buffer layer.