US 12,432,957 B2
HEMT transistor with gate extension
Jean-Claude Jacquet, Palaiseau (FR); Philippe Altuntas, Palaiseau (FR); Sylvain Delage, Palaiseau (FR); and Stéphane Piotrowicz, Palaiseau (FR)
Assigned to THALES, Courbevoie (FR)
Appl. No. 17/787,566
Filed by THALES, Courbevoie (FR)
PCT Filed Dec. 18, 2020, PCT No. PCT/EP2020/087322
§ 371(c)(1), (2) Date Jun. 20, 2022,
PCT Pub. No. WO2021/123382, PCT Pub. Date Jun. 24, 2021.
Claims priority of application No. 1915026 (FR), filed on Dec. 20, 2019.
Prior Publication US 2022/0406925 A1, Dec. 22, 2022
Int. Cl. H10D 30/47 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/475 (2025.01) [H10D 62/8503 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A high-mobility field-effect transistor operating at a frequency of between 10 and 80 GHz, comprising:
a stack along a Z axis, arranged on a substrate and comprising:
a buffer layer comprising a first semiconductor material comprising a binary or ternary or quaternary nitride compound and having a first bandgap,
a barrier layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound and having a second bandgap, the second bandgap being greater than the first bandgap,
a heterojunction between said buffer layer and said barrier layer, and
a two-dimensional electron gas localized in an XY plane and in the vicinity of the heterojunction,
a source(S), a drain (D), and a gate (G) arranged on an upper face of the barrier layer, between the source and the drain, a distance between the source and the drain being less than or equal to 4 μm, a gate length (Lg) being less than or equal to 0.5 μm,
a first dielectric layer (PL1) arranged at least on an upper surface of the barrier layer, between the gate (G) and the drain (D) and between the gate (G) and the source(S), having a relative permittivity εr and a thickness e which are such that: 0.5 nm≤e/εr≤2 nm,
a metal pad (PM) arranged between the gate (G) and the drain (D) and deposited on the first dielectric layer (PL1), said metal pad forming a structure having a length (Lp) and a foot in contact with the first dielectric layer, said length of the metal pad being less than or equal to 2 times the length (Lg) of the gate, the metal pad being electrically coupled to the gate by a first metal connection, a distance between the metal pad and the drain being greater than or equal to 300 nm and a distance between the metal pad and the gate being greater than or equal to 200 nm,
a sum of a surface of a cross section of the gate, a cross section of the metal pad and a cross section of the first metal connection connecting the gate and the metal pad (PM) is greater than or equal to two times a surface of a cross section (SG) of the gate (G), said cross sections being along an XZ plane.