US 12,432,949 B2
Manufacture of power MOSFETs
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GeneSic Semiconductor Inc., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/398,575.
Application 17/342,761 is a division of application No. 16/431,655, filed on Jun. 4, 2019, granted, now 11,075,277, issued on Jul. 27, 2021.
Application 18/398,575 is a continuation of application No. 17/342,761, filed on Jun. 9, 2021, granted, now 11,901,432.
Prior Publication US 2024/0128348 A1, Apr. 18, 2024
Int. Cl. H10D 62/832 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01)
CPC H10D 12/031 (2025.01) [H01L 21/0465 (2013.01); H01L 21/0475 (2013.01); H01L 21/0485 (2013.01); H01L 21/049 (2013.01); H10D 30/0295 (2025.01); H10D 30/66 (2025.01); H10D 62/155 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01); H10D 64/01 (2025.01); H10D 64/252 (2025.01); H10D 64/62 (2025.01); H10D 64/661 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a unit cell, the unit cell comprising:
a first conductivity type source region formed self-aligned within a second conductivity type first well region; a source trench extending through the first conductivity type source region and through at least a portion of the second conductivity type first well region, wherein the source trench is defined between a first vertical sidewall and a second vertical sidewall; a second conductivity type plug region positioned below the second conductivity type first well region and defined between a left boundary and a right boundary, wherein the first vertical sidewall is aligned with the left boundary and wherein the second vertical sidewall is aligned with the right boundary; and a silicide layer in contact with the first vertical sidewall and the second vertical sidewall;
wherein an active region is defined on a left side of a vertically oriented boundary extending through a thickness of the unit cell and a peripheral region is defined on a right side of the vertically oriented boundary, wherein the active region comprises a channel through which current carriers passes and wherein the source trench is entirely defined within the active region.