| CPC H10B 99/00 (2023.02) [H01L 23/5329 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a substrate including an active pattern comprising a first source/drain region and a second source/drain region that are spaced apart from each other;
a bit line that is electrically connected to the first source/drain region and crosses the active pattern;
a storage node contact electrically connected to the second source/drain region;
a spacer structure between the bit line and the storage node contact;
a landing pad electrically connected to the storage node contact; an insulating pattern on the spacer structure and adjacent to the landing pad; and
a liner between the insulating pattern and the landing pad, wherein the insulating pattern comprises:
an upper insulating portion;
a lower insulating portion between the upper insulating portion and the spacer structure; and
an inflection point defined between the upper insulating portion and the lower insulating portion on both sides of the insulating pattern in a cross-sectional view, and
wherein the largest width of the lower insulating portion is larger than the smallest width of the upper insulating portion, wherein the liner comprises an upper liner and a lower liner, wherein the lower liner wraps around a side surface and a bottom surface of the lower insulating portion.
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