US 12,432,938 B2
Memory array, memory, preparing method and writing method
Weisheng Zhao, Beijing (CN); Jingle Chen, Beijing (CN); Kaihua Cao, Beijing (CN); and Gefei Wang, Beijing (CN)
Assigned to BEIHANG UNIVERSITY, Beijing (CN)
Filed by BEIHANG UNIVERSITY, Beijing (CN)
Filed on Jul. 26, 2023, as Appl. No. 18/359,224.
Application 18/359,224 is a continuation of application No. PCT/CN2021/074299, filed on Jan. 29, 2021.
Prior Publication US 2024/0023347 A1, Jan. 18, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 61/00 (2023.01); H10B 80/00 (2023.01)
CPC H10B 80/00 (2023.02) [G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 61/22 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1443 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory array, comprising:
a plurality of memory cells arranged in an array and a conductor layer;
each of the memory cells comprising:
a write transistor configured to couple a first end thereof to top electrode wiring, the write transistor comprising at least one of a conventional transistor, a tunneling field effect transistor, a FinFET, or a vertical fully surrounding gate transistor; and
a magnetic tunnel junction (MTJ) configured to couple one end thereof close to a reference layer to a second end of the write transistor,
wherein, a side surface of the conductor layer is coupled to an end face close to a free layer, of each MTJ of each memory cell, respectively; two ends of the conductor layer are coupled to high-level wiring VDD and low-level wiring GND, respectively; the write transistors in each memory cell are integrated in a first wafer, the MTJs in each memory cell are integrated in a second wafer, and the first wafer and the second wafer are connected together by bonding, aiming to couple the writing transistors to corresponding MTJs.