US 12,432,937 B2
Semiconductor memory device with plurality of arrays
Hiroshi Nakaki, Yokkaichi Mie (JP); and Keisuke Nakatsuka, Kobe Hyogo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 7, 2023, as Appl. No. 18/179,976.
Claims priority of application No. 2022-090970 (JP), filed on Jun. 3, 2022.
Prior Publication US 2023/0397446 A1, Dec. 7, 2023
Int. Cl. H10B 80/00 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC H10B 80/00 (2023.02) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first memory cell array;
a second memory cell array arranged above the first memory cell array in a first direction; and
a row decoder,
wherein the first memory cell array includes:
a first select transistor;
a first memory cell;
a second select transistor, the first select transistor, the first memory cell, and the second select transistor being arranged along the first direction and coupled in series;
a first word line extending in a second direction crossing the first direction and coupled to the first memory cell;
a first select gate line extending in the second direction and coupled to a gate of the first select transistor; and
a second select gate line extending in the second direction and coupled to a gate of the second select transistor,
the second memory cell array includes:
a third select transistor;
a second memory cell;
a fourth select transistor, the third select transistor, the second memory cell, and the fourth select transistor being arranged along the first direction and coupled in series;
a second word line extending in the second direction and coupled to the second memory cell;
a third select gate line extending in the second direction and coupled to a gate of the third select transistor; and
a fourth select gate line extending in the second direction and coupled to a gate of the fourth select transistor,
the first word line and the second word line are commonly coupled to the row decoder,
the first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder,
the first memory cell array further includes:
a first contact plug extending in the first direction and provided on the first word line; and
a second contact plug passing through the first word line and the second select gate line and not electrically coupled to the first word line and the second select gate line,
the second memory cell array further includes
a third contact plug extending in the first direction and provided on the second word line, and
the first word line is electrically coupled to the second word line via the first contact plug, the second contact plug, and the third contact plug.