US 12,432,933 B2
Semiconductor packages
Hsiang-Ku Shen, Hsinchu (TW); Ku-Feng Lin, New Taipei (TW); Liang-Wei Wang, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 6, 2024, as Appl. No. 18/596,625.
Application 18/596,625 is a continuation of application No. 17/362,936, filed on Jun. 29, 2021, granted, now 11,950,432.
Claims priority of provisional application 63/156,943, filed on Mar. 5, 2021.
Prior Publication US 2024/0215261 A1, Jun. 27, 2024
Int. Cl. H10B 61/00 (2023.01); G11C 11/16 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [G11C 11/161 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first integrated circuit and a second integrated circuit, wherein the first integrated circuit comprises:
a first semiconductor substrate;
a first bonding structure bonded to the second integrated circuit;
a ferromagnetic layer surrounding the first bonding structure; and
a memory cell between the first semiconductor substrate and the first bonding structure.