US 12,432,932 B2
Semiconductor structure and manufacturing method thereof
Xiaoguang Wang, Hefei (CN); Dinggui Zeng, Hefei (CN); Huihui Li, Hefei (CN); and Kanyu Cao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Jun. 23, 2022, as Appl. No. 17/808,382.
Application 17/808,382 is a continuation of application No. PCT/CN2022/077806, filed on Feb. 25, 2022.
Claims priority of application No. 202111020119.1 (CN), filed on Sep. 1, 2021.
Prior Publication US 2023/0067509 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10D 30/67 (2025.01); H10D 99/00 (2025.01); H10N 50/01 (2023.01)
CPC H10B 61/22 (2023.02) [H10D 30/6728 (2025.01); H10D 30/6755 (2025.01); H10D 99/00 (2025.01); H10N 50/01 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a plurality of vertical transistors arranged in an aligned manner on the substrate; wherein a channel material of the vertical transistors comprises indium gallium zinc oxide;
a plurality of staggered contact pads connected to upper ends of the vertical transistors, wherein a single one of the staggered contact pads is connected to upper ends of an even number of the vertical transistors and a projection of the staggered contact pads on a surface of the substrate covers projections of the vertical transistors connected to the staggered contact pads on the surface of the substrate; and
a magnetic tunnel junction is arranged on the single one of the staggered contact pads.