US 12,432,928 B2
Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry
Hung-Wei Liu, Meridian, ID (US); Vassil N. Antonov, Boise, ID (US); Ashonita A. Chavan, Boise, ID (US); Darwin Franseda Fan, Boise, ID (US); Jeffery B. Hull, Boise, ID (US); Anish A. Khandekar, Boise, ID (US); Masihhur R. Laskar, Boise, ID (US); Albert Liao, Boise, ID (US); Xue-Feng Lin, Boise, ID (US); Manuj Nahar, Boise, ID (US); and Irina V. Vasilyeva, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 29, 2023, as Appl. No. 18/522,637.
Application 17/589,310 is a division of application No. 17/027,046, filed on Sep. 21, 2020, granted, now 11,264,395, issued on Mar. 1, 2022.
Application 18/522,637 is a continuation of application No. 17/589,310, filed on Jan. 31, 2022, granted, now 11,871,582.
Prior Publication US 2024/0164114 A1, May 16, 2024
Int. Cl. H10B 53/20 (2023.01); H01L 21/223 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 62/17 (2025.01)
CPC H10B 53/20 (2023.02) [H01L 21/223 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 53/30 (2023.02); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 62/292 (2025.01)] 22 Claims
OG exemplary drawing
 
1. Integrated circuitry comprising:
a substrate comprising insulative material;
a lower array above the substrate, the lower array comprising vertical transistors; the lower-array vertical transistors individually comprising a lower-array top source/drain region, a lower-array bottom source/drain region, a lower-array channel region vertically between the lower-array top and bottom source/drain regions, and a lower-array gate operatively laterally-adjacent the lower-array channel region;
an upper array of vertical transistors spaced above the lower array of vertical transistors, the upper-array vertical transistors individually comprising an upper-array top source/drain region, an upper-array bottom source/drain region, an upper-array channel region vertically between the upper-array top and bottom source/drain regions, and an upper-array gate operatively laterally-adjacent the upper-array channel region;
insulating material vertically between and spacing the lower and upper arrays relative one another;
the lower-array channel regions and the upper-array channel regions individually having an average concentration of elemental-form H of 0.005 to less than 1 atomic percent;
a lower-array gate insulator laterally-between the lower-array channel region and the lower-array gate;
the lower array comprising capacitors individually comprising a lower-array capacitor insulator between a pair of lower-array capacitor electrodes; and
at least one of (a) and (b), where:
(a): at least one of the lower-array vertical transistors having its lower-array gate insulator comprising a metal oxide, where the metal is one or more of Pb, Zr, Hf, Ru, and Ti; and
(b): at least one of the lower-array capacitors having its lower-array capacitor insulator comprising the metal oxide.