US 12,432,924 B2
Integrated circuitry and method used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US); and Alyssa N. Scarbrough, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 5, 2023, as Appl. No. 18/218,496.
Application 18/218,496 is a division of application No. 17/030,751, filed on Sep. 24, 2020, granted, now 11,744,069.
Claims priority of provisional application 63/070,979, filed on Aug. 27, 2020.
Prior Publication US 2023/0363163 A1, Nov. 9, 2023
Int. Cl. H01L 21/31 (2006.01); H10B 43/27 (2023.01); H01L 21/311 (2006.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/31116 (2013.01); H10B 43/10 (2023.02)] 8 Claims
OG exemplary drawing
 
1. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line; and
a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating first insulating tiers and second insulating tiers, the lower portion comprising:
a lowest insulator tier directly above conductor material of a conductor tier, the lowest insulator tier comprising solid carbon and nitrogen-containing material; and
an immediately-adjacent tier directly above the solid carbon and nitrogen-containing material of the lowest insulator tier, the immediately-adjacent tier comprising material that is of different composition from that of the lowest insulator tier.