US 12,432,922 B2
Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3D NAND devices
Hong Ma, Singapore (SG); Sha Tao, Dalian (CN); and Qun Li, Liaoning (CN)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Appl. No. 18/002,513
Filed by INTEL NDTM US LLC, Santa Clara, CA (US)
PCT Filed Jul. 23, 2020, PCT No. PCT/CN2020/103811
§ 371(c)(1), (2) Date Dec. 20, 2022,
PCT Pub. No. WO2022/016455, PCT Pub. Date Jan. 27, 2022.
Prior Publication US 2023/0232629 A1, Jul. 20, 2023
Int. Cl. H10B 43/27 (2023.01); G11C 16/04 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate including control circuitry therein;
a memory array electrically coupled to the control circuitry and including a plurality of word lines disposed to define a staircase structure, and a staircase etch stop layer including:
a sandwich etch stop layer disposed on a top region the staircase structure furthest from the substrate and including a first etch stop layer and a third etch stop layer made of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from those of the first material;
a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer;
a dielectric layer on the staircase etch stop layer; and
contact structures extending through the dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.