| CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |

|
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure comprising interleaved first dielectric layers and second dielectric layers;
forming channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure;
replacing all the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure with conductive layers; and
forming word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.
|