US 12,432,918 B2
Three-dimensional memory devices and methods for forming the same
Linchun Wu, Wuhan (CN); Kun Zhang, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wei Xie, Wuhan (CN); Di Wang, Wuhan (CN); Bingguo Wang, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jan. 6, 2022, as Appl. No. 17/570,091.
Application 17/570,091 is a continuation of application No. PCT/CN2021/138167, filed on Dec. 15, 2021.
Claims priority of application No. PCT/CN2021/114050 (WO), filed on Aug. 23, 2021.
Prior Publication US 2023/0056340 A1, Feb. 23, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers;
a channel structure extending through the stack structure along a first direction in contact with a source of the 3D memory device at a bottom portion of the channel structure, the channel structure comprising a semiconductor channel, and a memory film over the semiconductor channel, and the memory film comprising a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and
a polysilicon layer disposed under the stack structure,
wherein a first thickness of the blocking layer at the bottom portion of the channel structure is larger than a second thickness of the blocking layer at an upper portion of the channel structure, and the first thickness of the blocking layer or the second thickness of the blocking layer comprises dielectric materials formed between the storage layer and the stack structure along a second direction perpendicular to the first direction; and
the tunneling layer, the storage layer, and the blocking layer are in direct contact with the polysilicon layer.