| CPC H10B 41/41 (2023.02) [H01L 25/18 (2013.01); H10B 10/18 (2023.02); H10B 12/50 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 88/00 (2025.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09181 (2013.01)] | 20 Claims |
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1. A storage device comprising:
a first semiconductor structure including a first cell area, including a plurality of first memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area, the first cell area including gate electrodes stacked on the first semiconductor substrate, spaced apart from each other, and channel structures penetrating through the gate electrodes and connected to the first semiconductor substrate;
a second semiconductor structure including a peripheral circuit area disposed on a second semiconductor substrate and on which peripheral circuits for controlling the plurality of first memory cells are disposed, a second cell area including a plurality of second memory cells disposed adjacently to the peripheral circuit area, and a second metal pad bonded to the first metal pad; and
a third semiconductor structure including a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate and a connection structure penetrating through the second semiconductor substrate and connecting the memory controller to the second semiconductor structure, the memory controller controlling the first cell area and the second cell area based on a signal applied from a host through the third metal pad.
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