US 12,432,915 B2
Semiconductor device having a memory element with a source region and drain region and having multiple assistance elements
Hiroshige Hirano, Nara (JP); Hiroaki Kuriyama, Toyama (JP); and Atsushi Noma, Toyama (JP)
Assigned to TOWER PARTNERS SEMICONDUCTOR CO., LTD., Uozu (JP); and TOWER SEMICONDUCTOR LTD., Migdal Haemek (IL)
Filed by TOWER PARTNERS SEMICONDUCTOR CO., LTD., Uozu (JP); and TOWER SEMICONDUCTOR LTD., Migdal Haemek (IL)
Filed on May 27, 2022, as Appl. No. 17/827,589.
Claims priority of application No. 2021-203984 (JP), filed on Dec. 16, 2021.
Prior Publication US 2023/0200062 A1, Jun. 22, 2023
Int. Cl. H10B 41/41 (2023.01); G11C 16/14 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10D 30/68 (2025.01)
CPC H10B 41/41 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10D 30/684 (2025.01); H10D 30/6892 (2025.01); G11C 16/14 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell on a semiconductor substrate, the memory cell including a memory element, a first assistance element, and a second assistance element,
the memory element including a source region, a drain region, and a selection gate and a floating gate in series between the source region and the drain region,
the first assistance element including a first impurity region and a first gate on the semiconductor substrate, the first gate being electrically connected to the floating gate,
the second assistance element including a second impurity region and a second gate on the semiconductor substrate, the second gate being electrically connected to the floating gate, and
the second impurity region of the second assistance element being connected to a signal line that is connected to the drain region of the memory element or a signal line that is connected to the selection gate of the memory element.