| CPC H10B 41/30 (2023.02) [H10D 30/0243 (2025.01)] | 9 Claims |

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1. A non-volatile memory structure, comprising:
a substrate; and
a gate stack layer over the substrate, wherein the gate stack layer comprises:
an active pattern including a plurality of first active stacks and a plurality of second active stacks, wherein the plurality of first active stacks and the plurality of second active stacks are arranged separately in a first direction and extend in a second direction, wherein the second direction is different from the first direction; and
a rail block extending in the first direction, and having a first side and a second side opposite the first side, wherein the plurality of first active stacks connect the first side of the rail block, the plurality of second active stacks connect the second side of the rail block, and the first side of the rail block includes a plurality of first protruding portions arranged separately in the first direction.
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