| CPC H10B 41/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 17 Claims |

|
1. A semiconductor memory device comprising:
a semiconductor substrate including a first region and a second region;
a memory cell array over the first region of the semiconductor substrate;
a dummy stack structure over the second region of the semiconductor substrate;
a chip guard structure penetrating the dummy stack structure; and
a void-containing structure penetrating the dummy stack structure,
wherein the dummy stack structure extends to surround opposite sidewalls of the void-containing structure.
|