US 12,432,910 B2
Electrically programmable fuse over lateral bipolar transistor
Anindya Nath, Essex Junction, VT (US); Ephrem G. Gebreselasie, South Burlington, VT (US); Rajendran Krishnasamy, Essex Junction, VT (US); and Alain F. Loiseau, Williston, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,156.
Prior Publication US 2024/0074167 A1, Feb. 29, 2024
Int. Cl. H10B 20/20 (2023.01); H01L 23/525 (2006.01); H10D 10/60 (2025.01)
CPC H10B 20/20 (2023.02) [H01L 23/5256 (2013.01); H10D 10/60 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A structure comprising:
a lateral bipolar transistor within a semiconductor layer and over a substrate;
an insulator layer over a portion of the semiconductor layer, wherein a separation distance between an emitter of the lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the lateral bipolar transistor and a second sidewall of the insulator layer; and
an electrically programmable fuse (efuse) structure within a polycrystalline semiconductor layer and over the insulator layer, wherein the efuse structure is over a current path through the lateral bipolar transistor, and the insulator layer electrically isolates the efuse structure from the current path.
 
7. A structure comprising:
a crystalline semiconductor layer over a substrate;
a lateral bipolar transistor defined within the crystalline semiconductor layer;
an insulator layer over a portion of the crystalline semiconductor layer, wherein a separation distance between an emitter of the lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the lateral bipolar transistor and a second sidewall of the insulator layer;
a polycrystalline semiconductor layer on the insulator layer; and
an electrically programmable fuse (efuse) structure defined within the polycrystalline semiconductor layer and over the insulator layer, wherein a vertical thickness of the insulator layer electrically isolates the efuse structure and the lateral bipolar transistor, and wherein the efuse structure is over a current path through the lateral bipolar transistor.
 
12. A structure comprising:
a first lateral bipolar transistor within a semiconductor layer and over a substrate;
an insulator layer over a portion of the semiconductor layer, wherein a separation distance between an emitter of the first lateral bipolar transistor and a first sidewall of the insulator layer is larger than a separation distance between a collector of the first lateral bipolar transistor and a second sidewall of the insulator layer;
a second lateral bipolar transistor within a polycrystalline semiconductor layer and over the insulator layer; and
an electrically programmable fuse (efuse) structure within the polycrystalline semiconductor layer and over the insulator layer, wherein a cathode of the efuse structure is adjacent one of an emitter and a collector of the second lateral bipolar transistor, and the efuse structure is over a current path through the first lateral bipolar transistor, and the insulator layer electrically isolates the efuse structure from the current path.