US 12,432,909 B2
Semiconductor memory device having an ohmic contact on the impurity regions
Junhyeok Ahn, Suwon-si (KR); Woojin Jeong, Suwon-si (KR); and Hui-Jung Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 5, 2023, as Appl. No. 18/093,561.
Claims priority of application No. 10-2022-0042425 (KR), filed on Apr. 5, 2022.
Prior Publication US 2023/0320080 A1, Oct. 5, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
an active portion defined by a device isolation pattern, the active portion comprising a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion;
a word line provided on the active portion and extending in a first direction;
a bit line provided on the word line and extending in a second direction crossing the first direction;
a bit line contact provided between the bit line and the first impurity region of the active portion;
a storage node pad provided on the second impurity region of the active portion;
a storage node contact provided on the storage node pad and at a side of the bit line; and
an ohmic contact layer provided in at least one of a first region between the first impurity region and the bit line and a second region between the second impurity region and the storage node contact,
wherein the ohmic contact layer comprises a two-dimensional material.