| CPC H10B 12/315 (2023.02) [H10B 12/03 (2023.02); H10B 12/485 (2023.02)] | 12 Claims |
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1. A memory device, comprising:
a memory cell array comprising gate structures formed on a substrate, first active regions adjacent to the gate structures, gate insulating layers disposed between the gate structures and the first active regions, and cell capacitors connected to the first active regions and extending in a vertical direction with respect to a surface of the substrate;
a first dummy capacitor and a second dummy capacitor extending in a first direction and in the vertical direction, and disposed to be adjacent to the memory cell array in a second direction intersecting the first direction, the first direction and the second direction being parallel to the surface of the substrate;
a third dummy capacitor extending in the second direction and the vertical direction and disposed to be adjacent to the memory cell array in the first direction;
a fourth dummy capacitor extending in the second direction and the vertical direction and disposed to be adjacent to the memory cell array in the first direction;
one or more upper contacts overlapping, in the vertical direction, the first dummy capacitor, the second dummy capacitor, and the third dummy capacitor; and
an upper conductive layer in contact with the one or more upper contacts and is disposed to cover upper surfaces of the cell capacitors,
wherein the memory cell array is disposed between the first dummy capacitor and the second dummy capacitor,
wherein the memory cell array is disposed between the third dummy capacitor and the fourth dummy capacitor.
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