US 12,432,898 B2
Memory device having tiers of 2-transistor memory cells
Kamal M. Karda, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); Haitao Liu, Boise, ID (US); and Karthik Sarpatwari, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 28, 2023, as Appl. No. 18/521,273.
Claims priority of provisional application 63/429,784, filed on Dec. 2, 2022.
Prior Publication US 2024/0188273 A1, Jun. 6, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 11/405 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/00 (2023.02) [G11C 11/405 (2013.01); G11C 11/4096 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first conductive structure, a second conductive structure, and a third conductive structure, each of the first, second, and third conductive structures having a length in a first direction;
a first memory cell and a second memory cell located at a distance from the first memory cell in a second direction perpendicular to the first direction, each of the first and second memory cells including:
a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures; and
a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures;
a first conductive region located on a third level of the apparatus and opposite the first semiconductor portion of the first memory cell;
a first additional conductive region located on a fourth level of the apparatus and opposite the second semiconductor portion of the first memory cell;
a second conductive region located on the third level and opposite the first semiconductor portion of the second memory cell, the second conductive region electrically separated from the first conducive region; and
a second additional conductive region located on the fourth level and opposite the second semiconductor portion of the second memory cell, the second additional conductive region electrically separated from the first additional conducive region.