US 12,432,859 B2
Surface mount device bonded to an inner layer of a multi-layer substrate
Kelvin Tan Aik Boo, George Town (MY); Chin Hui Chong, Braddell Hill (SG); Seng Kim Ye, Fernvale Close (SG); Hong Wan Ng, Singapore (SG); and Hem P. Takiar, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 28, 2023, as Appl. No. 18/215,711.
Application 18/215,711 is a continuation of application No. 17/012,817, filed on Sep. 4, 2020, granted, now 11,723,150.
Prior Publication US 2023/0345639 A1, Oct. 26, 2023
Int. Cl. H05K 1/18 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2023.01)
CPC H05K 1/183 (2013.01) [H01L 23/13 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/642 (2013.01); H01L 25/0657 (2013.01); H05K 1/181 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10159 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a secondary layer of a substrate comprising a first open area that extends through the secondary layer to a first inner layer of the substrate, the secondary layer comprising a plurality of electrical contacts located on an exterior surface of the secondary layer and configured to couple to another substrate; and
the first inner layer of the substrate that is positioned between a primary layer and the secondary layer;
a first plurality of component bond pads that are disposed on the first inner layer and that are exposed via the first open area of the secondary layer;
a first electrical component mounted on the first plurality of component bond pads;
the primary layer of the substrate comprising an exterior surface, wherein the exterior surface of the primary layer faces opposite the exterior surface of the secondary layer, and wherein the primary layer comprises a second open area that extends through the primary layer to a second inner layer of the substrate;
a second plurality of component bond pads disposed on the second inner layer and that are exposed via the second open area of the primary layer;
a second electrical component mounted on the second plurality of component bond pads;
a first integrated circuit (IC) die disposed on the exterior surface of the primary layer;
a second IC die stacked on the first IC die;
bond wires coupling to the first IC die to the primary layer; and
a packaging material disposed above the primary layer, the first IC die, the second IC die and the second electrical component, wherein the packing material encapsulates the exterior surface of the primary layer, the first IC die, the second IC die, and the second electrical component.