US 12,432,849 B2
Flip-chip bonding structure and circuit board thereof
Chun-Te Lee, Hsinchu County (TW); Chih-Ming Peng, Taichung (TW); Pi-Yu Peng, Hsinchu County (TW); and Hui-Yu Huang, Hsinchu (TW)
Assigned to CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed by CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed on Apr. 13, 2023, as Appl. No. 18/134,082.
Claims priority of application No. 111205206 (TW), filed on May 19, 2022.
Prior Publication US 2023/0380053 A1, Nov. 23, 2023
Int. Cl. H05K 1/02 (2006.01); H01L 21/60 (2006.01); H05K 1/03 (2006.01); H05K 3/00 (2006.01)
CPC H05K 1/0266 (2013.01) [H01L 21/60 (2021.08); H05K 1/03 (2013.01); H05K 3/0044 (2013.01); H01L 2021/60022 (2013.01); H05K 2201/10893 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A flip-chip bonding structure comprising:
a chip including a plurality of first bumps and a plurality of second bumps; and
a circuit board including:
a light-transmissive substrate including a first surface and a second surface;
a first circuit group disposed on the first surface and including a plurality of first leads, each of the plurality of first leads includes a first bonding portion and projects a first lead shadow on the second surface, there is a first gap between the adjacent first leads, each of the plurality of first bumps is configured to be bonded to the first bonding portion of one of the plurality of first leads and projects a first bump shadow on the second surface;
a second circuit group disposed on the first surface and including a plurality of second leads, each of the plurality of second leads includes a second bonding portion and projects a second lead shadow on the second surface, there is a second gap between the adjacent second leads, the second gap is not equal to the first gap, each of the plurality of second bumps is configured to be bonded to the second bonding portion of one of the plurality of second leads and projects a second bump shadow on the second surface;
a boundary circuit disposed on the first surface and located between the first and second circuit groups, the boundary circuit projects a boundary circuit shadow on the second surface; and
an identifying member located on the second surface, wherein the boundary circuit shadow and the identifying member are configured to be passed through by a vertical imaginary line.