US 12,432,847 B2
Circuit element
Hiroaki Ikeuchi, Yokohama Kanagawa (JP); and Keiichi Yamaguchi, Kawasaki Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Feb. 22, 2023, as Appl. No. 18/172,997.
Claims priority of application No. 2022-140941 (JP), filed on Sep. 5, 2022.
Prior Publication US 2024/0080968 A1, Mar. 7, 2024
Int. Cl. H05K 1/18 (2006.01); H01G 4/12 (2006.01); H01G 4/33 (2006.01); H01L 23/66 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/0243 (2013.01) [H01G 4/12 (2013.01); H01G 4/33 (2013.01); H01L 23/66 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit element comprising:
a silicon substrate;
a lower electrode formed on a major surface of the silicon substrate by a doping process;
a dielectric film formed on the lower electrode;
an upper electrode formed on the dielectric film, the upper electrode including a slit;
a first pad electrically connected to the lower electrode; and
a second pad electrically connected to the upper electrode,
wherein an outer shape of the upper electrode is a rectangular shape with a long side extending between the first pad and the second pad.