| CPC H04W 74/0841 (2013.01) [H04W 72/0446 (2013.01); H04W 72/1263 (2013.01); H04W 74/0866 (2013.01)] | 27 Claims |

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1. A device comprising:
an interface circuit, wherein the interface circuit is arranged to transmit a first signal;
a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to provide the first signal so as to comprise a random access preamble,
wherein the processor circuit is arranged to select the random access preamble such that the random access preamble is associated with a transmission information,
wherein the processor circuit is arranged to transmit a second signal after transmitting the first signal,
wherein the second signal comprises second information related to the transmission information,
wherein the processor circuit is arranged to transmit a contention resolution signal between transmitting the first signal and transmitting the second signal.
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