| CPC H04W 24/08 (2013.01) [H04W 72/0453 (2013.01); H04W 72/23 (2023.01); H04W 72/56 (2023.01)] | 23 Claims |

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1. A user equipment (UE), comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to cause the UE to:
receive a message indicating a plurality of CORESETs, wherein each CORESET of the plurality of CORESETs comprises one or more quasi-co-location (QCL)-Type-D properties and is associated with a respective physical downlink control channel (PDCCH) monitoring occasion of a plurality of overlapping PDCCH monitoring occasions, and wherein one or more respective PDCCH candidates correspond to the respective PDCCH monitoring occasion;
receive, on one or more component carriers (CCs) in a same band, a plurality of simultaneous beams comprising a plurality of PDCCH candidates;
exclude, from the plurality of CORESETs, each CORESET comprising a single QCL-Type-D property based on one or more CORESETs of the plurality of CORESETs comprising two QCL-Type-D properties;
prioritize the plurality of CORESETs after excluding each CORESET comprising the single QCL-Type-D property; and
monitor a set of PDCCH candidates of the plurality of PDCCH candidates associated with: a first CORESET of the plurality of CORESETs comprising a first QCL-Type-D property, a second CORESET of the plurality of CORESETs comprising a second QCL-Type-D property, and a set of monitoring CORESETs of the plurality of CORESETs each associated with one or both of the first QCL-Type-D property or the second QCL-Type-D property based on a number of QCL-Type-D properties of the respective monitoring CORESET, wherein the first CORESET is a highest priority CORESET based on a set of priority rules.
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