US 12,432,026 B2
Quasi co-location determination for overlapping downlink channels and synchronization blocks
Mostafa Khoshnevisan, San Diego, CA (US); Yan Zhou, San Diego, CA (US); Xiaoxia Zhang, San Diego, CA (US); and Tao Luo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 10, 2022, as Appl. No. 17/741,220.
Claims priority of provisional application 63/187,130, filed on May 11, 2021.
Prior Publication US 2022/0368486 A1, Nov. 17, 2022
Int. Cl. H04L 5/00 (2006.01); H04W 72/0446 (2023.01)
CPC H04L 5/0048 (2013.01) [H04L 5/0094 (2013.01); H04W 72/0446 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A user equipment (UE), comprising:
at least one processor; and
at least one memory coupled with the at least one processor, the at least one memory storing instructions executable by the at least one processor to cause the UE to:
determine a first physical layer cell identifier corresponding to a serving cell configured for the UE and a second physical layer cell identifier corresponding to a second cell configured for the UE different than the serving cell;
receive a synchronization signal block associated with a physical layer cell identifier corresponding to the serving cell or the second cell, the physical layer cell identifier comprising the first physical layer cell identifier or the second physical layer cell identifier;
determine a quasi co-location with TypeD relationship between the synchronization signal block and one or more downlink channels that are overlapping in time with the synchronization signal block based at least in part on the one or more downlink channels being associated with the physical layer cell identifier that is associated with the synchronization signal block; and
process a first downlink channel of the one or more downlink channels based at least in part on the quasi co-location with TypeD relationship.