US 12,431,909 B2
SSD with reference clock loss tolerant oscillator
Nitin Gupta, Uttar Pradesh (IN); Pikul Sarkar, Karnataka (IN); and Bhavin Odedara, Karnataka (IN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 10, 2023, as Appl. No. 18/349,906.
Claims priority of provisional application 63/387,622, filed on Dec. 15, 2022.
Prior Publication US 2024/0201848 A1, Jun. 20, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 16/32 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/099 (2013.01) [G11C 16/32 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a memory die; and
a controller including an oscillator circuit that comprises a clock generation circuit and a clock selection circuit, configured to:
generate, via the clock generation circuit, a clock based on a host reference clock,
select, via the clock selection circuit, an output clock from the host reference clock or the generated clock, and
output the output clock to the memory die;
wherein while the host reference clock is available, the output clock includes a frequency that is identical to a frequency or a division factor of the frequency of the host reference clock, and in response to loss of the host reference clock, the oscillator circuit is configured to reduce the frequency of the output clock to a frequency of the generated clock within a generated clock cycle following the loss of the host reference clock.