US 12,431,907 B1
Duty-cycle matched differential clock divider circuit
Ryan Anthony Scott, Fenwick (CA); and James Lin, Richmond Hill (CA)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 6, 2023, as Appl. No. 18/329,815.
Int. Cl. H03K 21/02 (2006.01); H03K 3/037 (2006.01)
CPC H03K 21/023 (2013.01) [H03K 3/0372 (2013.01); H03K 21/026 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A differential clock frequency divider circuit, comprising:
a primary latch including a single data input terminal and a single data output terminal, the primary latch coupled to receive a feedback signal at the single data input terminal and complementary input clock signals, the primary latch producing a first output signal at the single data output terminal;
a differential latch, coupled to receive the first output signal produced by the primary latch and the complementary input clock signals, the differential latch producing a second output signal and a third output signal; and
a first inverter, coupled to receive the second output signal, the first inverter producing the feedback signal applied to the single data input terminal of the primary latch.