US 12,431,903 B2
Freeze and clear logic circuits and methods for integrated circuits
Sadegh Yazdanshenas, Toronto (CA); and Jeffrey Chromczak, Toronto (CA)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 24, 2022, as Appl. No. 17/703,974.
Prior Publication US 2022/0216873 A1, Jul. 7, 2022
Int. Cl. H03K 19/177 (2020.01); H03K 19/20 (2006.01)
CPC H03K 19/177 (2013.01) [H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a programmable logic circuit;
freeze logic circuitry comprising a first input coupled to receive a freeze signal and a second input coupled to receive a control signal;
second logic circuitry comprising a first input coupled to a first output of the programmable logic circuit and a second input coupled to an output of the freeze logic circuitry, wherein the freeze logic circuitry drives an output signal of the second logic circuitry to a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit; and
clear logic circuitry that generates the control signal in response to a clear signal, wherein the freeze logic circuitry drives the output signal of the second logic circuitry to the predefined logic state in response to the control signal being asserted after the power-up of the integrated circuit.