US 12,431,719 B2
Semiconductor device and operating method of semiconductor device
Yuki Okamoto, Kanagawa (JP); and Takahiko Ishizu, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/269,330
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Aug. 21, 2019, PCT No. PCT/IB2019/057027
§ 371(c)(1), (2) Date Feb. 18, 2021,
PCT Pub. No. WO2020/044168, PCT Pub. Date Mar. 5, 2020.
Claims priority of application No. 2018-163168 (JP), filed on Aug. 31, 2018; application No. 2018-201005 (JP), filed on Oct. 25, 2018; application No. 2018-219225 (JP), filed on Nov. 22, 2018; and application No. 2018-239852 (JP), filed on Dec. 21, 2018.
Prior Publication US 2021/0242690 A1, Aug. 5, 2021
Int. Cl. H02J 7/00 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01M 10/42 (2006.01); H01M 10/44 (2006.01); H01M 10/48 (2006.01)
CPC H02J 7/0014 (2013.01) [H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01); H01M 10/425 (2013.01); H01M 10/441 (2013.01); H01M 10/48 (2013.01); H01M 2010/4271 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first cell-balance circuit;
a second cell-balance circuit;
a voltage generation circuit;
a first secondary battery electrically connected to the first cell-balance circuit; and
a second secondary battery electrically connected to the second cell-balance circuit,
wherein the first cell-balance circuit comprises:
a first comparison circuit;
a first terminal electrically connected to a non-inverting input terminal of the first comparison circuit;
a first transistor comprising a metal oxide comprising indium in a channel formation region, one of a source and a drain of the first transistor electrically connected to an inverting input terminal of the first comparison circuit;
a first capacitor, one electrode of the first capacitor electrically connected to the inverting input terminal of the first comparison circuit;
a second terminal electrically connected to the other electrode of the first capacitor; and
a third terminal electrically connected to the other one of the source and the drain of the first transistor,
wherein a positive electrode of the first secondary battery is electrically connected to the first terminal,
wherein a negative electrode of the first secondary battery is electrically connected to the second terminal,
wherein the second cell-balance circuit comprises:
a second comparison circuit;
the second terminal is electrically connected to a non-inverting input terminal of the second comparison circuit;
a second transistor comprising a metal oxide comprising indium in a channel formation region, one of a source and a drain of the second transistor electrically connected to an inverting input terminal of the second comparison circuit;
a second capacitor, one electrode of the second capacitor electrically connected to the inverting input terminal of the second comparison circuit;
a fourth terminal electrically connected to the other electrode of the second capacitor; and
a fifth terminal electrically connected to the other one of the source and the drain of the second transistor,
wherein a positive electrode of the second secondary battery is electrically connected to the second terminal,
wherein a negative electrode of the second secondary battery is electrically connected to the fourth terminal,
wherein the voltage generation circuit comprises a third transistor and a third capacitor,
wherein one electrode of the third capacitor is electrically connected to one of a source and a drain of the third transistor,
wherein the second terminal is electrically connected to the other of the source and the drain of the third transistor,
wherein the voltage generation circuit is configured to generate a voltage, the voltage is supplied from the third terminal, and
wherein the third transistor comprises a metal oxide comprising indium in a channel formation region.